Raw status interrupt of channel0
| OUT_DONE_CH_INT_RAW | The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0. |
| OUT_EOF_CH_INT_RAW | The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0. |
| OUT_DSCR_ERR_CH_INT_RAW | The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0. |
| OUT_TOTAL_EOF_CH_INT_RAW | The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0. |
| OUTFIFO_L1_OVF_CH_INT_RAW | This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. |
| OUTFIFO_L1_UDF_CH_INT_RAW | This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. |
| OUTFIFO_L2_OVF_CH_INT_RAW | This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. |
| OUTFIFO_L2_UDF_CH_INT_RAW | This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. |
| OUTFIFO_L3_OVF_CH_INT_RAW | This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. |
| OUTFIFO_L3_UDF_CH_INT_RAW | This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. |